Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data, such as a basic input/output system (BIOS), are typically stored in flash memory devices for use in personal computer systems.
As the performance and complexity of electronic systems increase, the requirement for additional memory in a system also increases. However, in order to continue to reduce the costs of the system, it is desirable to keep the parts count low. This can be accomplished by increasing the memory density of an integrated circuit by using such technologies as multilevel cells (MLC). For example, MLC NAND flash memory is a cost effective non-volatile memory.
In a NAND type memory array architecture, the floating gate memory cells of the memory array are arranged in a matrix of rows and columns. The memory cells of the array are also arranged together in strings, typically of 8, 16, 32, or more each, where the memory cells in the string are connected together in series, source to drain, between a common source line and a column bit line. The array is then accessed by a row decoder activating a row of floating gate memory cells by selecting the word line connected to their gates. In addition, bit lines can also be driven high or low depending on the current operation being performed.
Multilevel memory cells take advantage of the analog nature of a traditional flash cell by assigning a data state (e.g., as represented by a bit pattern) to a specific range of threshold voltages (Vt) stored on the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of threshold voltage ranges assigned to the cell and the stability of the assigned threshold voltage ranges during the lifetime operation of the memory cell. The number of threshold voltage ranges, which are sometimes also referred to a Vt distribution windows, used to represent a bit pattern comprised of N-bits is 2N. FIG. 1 illustrates an example of threshold voltage ranges 112, 114, 116, 118 as they might be assigned for a multiple level memory cell.
For example, a cell may be assigned a Vt that falls within one of four different voltage ranges 112, 114, 116, 118 of 200 mV, each being used to represent a data state corresponding to a bit pattern comprised of two bits. For example, the threshold voltage distribution 104 illustrates the range of threshold voltages 114 for multilevel memory cells assigned a data state of ‘10’. Typically, a dead space (which is also sometimes referred to as a margin) 110 of 0.2V to 0.4V is maintained between each range to keep the Vt distributions from overlapping. If the voltage stored on the cell is within the first Vt distribution 102, the cell in this example is storing a logical ‘11’ state and is typically considered the erased state of the cell. If the voltage is within the second Vt distribution 104, the cell in this example is storing a logical ‘10’ state. A voltage in the third distribution 106 would indicate that the cell in this example is storing a logical ‘00’ state. Finally, a voltage in the fourth distribution 108, in this example, indicates that a logical ‘01’ state is stored in the cell.
During programming of an individual multilevel cell, the cell's Vt is altered by moving, e.g., shifting, the Vt of the cell to fall within the threshold voltage distribution representative of the desired data value for that cell. However, MLC devices are generally more prone to program disturb issues where each cell may be subjected to multiple program operations to reach its desired Vt distribution. Multiple program operations are the result of programming one bit during each program operation. For example, a two-bit MLC may require two program operations to adjust the Vt to its desired state while a three-bit MLC may require three program operations to adjust the Vt to its desired state.
For the reasons stated above, and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives to existing programming schemes for MLC NAND flash memory devices.